`include "defines.v"
`timescale 1ns / 1ns
module inst_ram(
    input wire rst,
    input wire[`InstAddrBus] instaddr_i,
    output reg[`InstBus] inst_o
);
    reg[`MemBus] ram_[0:`MemNum - 1];
    always @ (*) 
    begin
        if (rst == `RstEnable)
            begin
                inst_o = `ZeroWord;
            end
        else
            begin
                inst_o = ram_[instaddr_i[31:2]];
            end
    end


endmodule